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The following odds and ends bits of code will run on their own, thanks to the mandatory test plans we were required to include with all our assignments. They were written in C++ for my CSE 120 class here at Penn State, which is otherwise known as intermediate programming. They have been successfully compiled and executed with GCC 2.95.3 on my 500 mhz iBook running Mac OSX. There's nothing genius material here, and the only really interesting code here might be the two ADTs and the Theatre Manager program, which was our final project.

The next class I took that involved programming was CSE 331, an introduction to hardware. Instead of C++, we learned MIPS assembler and VHDL. The MIPS wasn't terribly exciting, and it wasn't the focus of the class so there isn't much of it that I had to turn in. The real interesting project here was our last assignment, which was to build a single cycle MIPS processor with reduced instruction support (only 9). I realize there aren't many comments in most of the VHDL components. I did comment them, but as part of a much larger file that I handed in for my final grade. I will replace these files with commented versions soon. In the meantime, check them out.

  • Clock - Clock with 300 ns cycle.
  • PC - Simple memory that stores the value of PC and accepts inputs on a negative clock edge.
  • 2x1 Mux - Select 1 bit from a 2 bit input using a 1 bit select line.
  • 4x1 Mux - Select 1 bit from a 4 bit input using a 2 bit select line. Relies on 2x1 Mux.
  • 5x2 Mux - Select from one of two 5 bit inputs using a 2 bit select line.
  • 32x2 Mux - Select from one of two 32 bit inputs using a 2 bit select line.
  • Register File - Supports reads and writes to a MIPS register file, properly initialized.
  • 1 Bit Full Adder - Written completely in NAND, NOR, and NOT logic gates
  • 32 Bit Full Adder - Takes 2 32 bit inputs, adds them together, and produces a 32 bit output. Cin and Cout supported.
  • 1 Bit ALU (not significant bit) - A 1 Bit ALU that supports addition, subtraction, BEQ, NOR, SLT, and XOR instructions. Relies on 1 Bit Adder and 4x1 Mux.
  • 1 Bit ALU (significant bit) - A 1 Bit ALU that provides extra circuitry to detect overflow and handle SLT instructions. Relies on 1 Bit Adder and 4x1 Mux.
  • 32 Bit ALU - A 32 bit ripple adder ALU that supports addition, subtraction, BEQ, XOR, NOR, and SLT and includes overflow detection. Relies on 1 Bit ALU (significant bit), 1 Bit ALU (not significant bit), and Detect 0.
  • Detect 0 - Accepts a 32 bit input and determines if any of those bits are 0, and if so, outputs 1 as a flag. It was designed for BEQ detection.
  • Instruction Memory - Read comments to see what commands are already stored in the instruction memory. Find a MIPS assembler reference to learn how to encode your own.
  • Data Memory - Only set up and initialized to support 8 32 bit words right now. Supports reads and writes.
  • Main Control Unit - Takes the first 6 bits of a MIPS instruction and produces 1 bit control signals and a 2 bit ALU op code signal that control which components are activated during a clock cycle.
  • ALU Control Unit - Takes the last 6 bits of an R-Type instruction along with a 2 bit op code from the Main Control Unit and produces a 3 bit op code of its own to drive the ALU.
  • Full MIPS Processor - Supports the following subset of MIPS instructions: add, subtract, BEQ, XOR, NOR, SLT, LW, SW, and jump. Contains components similar to those above, but modified to only write on a negative clock edge. All requirements satisfied in file. (This is the culmination of everything above.)

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